As a method for insulating elements of a semiconductor device, the shallow trench isolation (STI) process has recently been used to form a shallow trench through etching or photolithography, and to deposit a dielectric layer to fill the trench. As one step of the STI process, a planarization process is included for removing steps caused by an excessive amount of insulating material, and recently, the chemical mechanical polishing (CMP) method is the most widely employed method for this planarization process.
The CMP process is one of the methods commonly used for planarizing semiconductor devices, such as flash memory devices and the like, as a surface planarization process. In the CMP process, a wafer to be subjected to the planarization process is placed on a rotating plate, a surface of the wafer is placed in contact with the pad of a polisher, and then the rotating plate and the pad of the polisher are rotated together with the supply of a slurry to perform the polishing process. In other words, the slurry flows between a wafer surface and the pad, such that polishing of the wafer surface is performed by mechanical friction caused by polishing particles in the slurry and surface protrusions of the pad, while chemical removal is simultaneously performed by chemical reaction between the chemical components in the slurry and the wafer surface.
In the CMP process, the rotating polishing pad and the wafer come into direct contact with each other through pressure, and a polishing slurry is provided on the interfaces thereof. Therefore, the wafer surface is mechanically and chemically polished by the polishing pad to which the slurry is applied and thereby becomes flat, and the characteristics such as the polishing speed, defects on the polishing surface, dishing, erosion, and the like, differ according to the composition of the slurry.
The CMP process has been successfully applied to the planarization of dielectrics such as silicon oxide films, silicon nitride films, and the like, for a long time, and has been actively applied even to the planarization process for metal films such as tungsten (W), aluminum (Al), copper (Cu), or the like.
However, selective slurries for use with tungsten films have a problem in that erosion inevitably occurs in regions where the tungsten wiring is densified after polishing. A silicon oxide film is deposited as an insulating film on a substrate for manufacturing semiconductor devices, and a titanium (Ti)-based diffusion barrier film and a tungsten film are formed after a metal wiring or plug pattern is formed. When the metal wiring or the plug is formed by a CMP process using a selective slurry on the substrate for manufacturing semiconductor devices, severe erosion is caused by the difference in polishing speed between the tungsten film and the insulating film.
Therefore, there is a demand to provide a novel CMP slurry capable of maintaining a precise balance between surface chemical etching and surface passivation to prevent unnecessary and excessive partial etching while providing effective polishing efficiency and polishing selectivity for tungsten and various other films.